The present invention relates to a nonvolatile, integrated-circuit memory array such as a flash erasable, electrically programmable read-only-memory (flash EPROM or flash EEPROM) array. In particular, the invention relates to control of the programming and erasing of a flash EPROM memory array.
Flash EPROMs of the type discussed herein are described in: (a) "A Single Transistor EEPROM cell and its implementation in a 512K CMOS EEPROM", S. Mukherjee et al., IEDM 1985 (p. 616-619) and in (b) "A 90ns 100K Erase/Program Cycle Megabit Flash Memory", V. Kynett et al., ISSCC 1989 (p. 140-141). The topic of reference (a) is also discussed in U.S. Pat. No. 4,698,787.
As flash memory technology continues to evolve, the demand for increasing ease of use has resulted in development of automated instructions for programming and erasing flash EPROMs. The automated program and erase instructions are embedded in the Write-State-Machine architecture of such flash EPROMs. The codes for those instructions are, for example, stored in a Control-Read-Only-Memory in the Write-State-Machine. The codes may include about 400 words of program and erase instructions and the Control-Read-Only-Memory may, for example, be mask-programmed with those codes during manufacture using any one of several known methods.
The proper functioning of the Control-Read-Only-Memory is crucial to the operation of flash EPROMs. Therefore, it is necessary to verify after manufacture that the Control-Read-Only-Memory is, in fact, programmed properly. However, because the Control-Read-Only-Memory is embedded in the Write-State-Machine, the Control-Read-Only-Memory inputs and outputs are not directly accessible for that verification testing. Even though the Control-Read-Only-Memory is not large (having perhaps 9 inputs and 50 outputs), the large number of outputs makes test observation difficult.
Compact testing methods, or testing methods based on checking an output function derived from a response rather than the response itself, are discussed in Abramovici et al., "Digital Systems Testing and Testable Design", Computer Science Press, New York (1990). Such derived output functions are sometimes called "signatures", or compressed representations of the true responses. Compact testing methods, or Built-In-Self-Test (BIST) architectures, generally require less memory than true-response test methods. One such compact testing method uses Built-In-Logic-Block-Observation (BILBO) registers and is discussed in Section 11.4.12 of the foregoing Abramovici et al. reference. The basic Built-In-Logic-Block-Observation Built-In-Self-Test architecture consists of partitioning a circuit into a set of registers and blocks of combinational logic, where the normal registers are replaced by Built-In-Logic-Block-Observation registers. In Built-In-Logic-Block-Observation register design, the inverted output of a storage cell is connected via a NOR and an exclusive OR gate to the data input of the next cell.
One of the problems associated with programming and erasing flash EPROMs is that significant silicon area is consumed by a Linear-Feedback-Shift-Register used for pulse timing. Another problem is that significant test time is required for verification of the contents of the Control-Read-Only-Memory because each programmed word must be separately scanned out. There is a need to conserve silicon area and to decrease the time required for verifing the Control-Read-Only-Memory contents.